Performance Improvement of Spacer engineered N-type Tree Shaped NSFET towards Advanced Technology nodes

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dc.contributor.authorGowthami, U
dc.contributor.authorPanigrahy, A
dc.contributor.authorRani, D
dc.contributor.authorBhukya, M
dc.contributor.authorSreenivasulu, V
dc.date.accessioned2024-10-09T06:16:42Z
dc.date.available2024-10-09T06:16:42Z
dc.date.issued2024
dc.description.abstractTree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high-k dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with T(NS) = 5 nm, W(NS) = 25 nm, WIB = 5 nm, and HIB = 25 nm has high on-current (ION) and low off-current (IOFF). The 3D device with single-k and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual-k device achieves the maximum ION/IOFF ratio, which is 109 , compared to 107 because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device's analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL = 23 mV/V and SS = 62 mV/dec and switching ratio (ION/IOFF) = 109 . The device's performance confirms that Moore's law holds even for lower technology nodes, allowing for further scalability.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/1605
dc.titlePerformance Improvement of Spacer engineered N-type Tree Shaped NSFET towards Advanced Technology nodesen_US
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