Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

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dc.contributor.authorPanigrahy, A
dc.contributor.authorAmudalapalli, V
dc.contributor.authorRani, D
dc.contributor.authorBhukya, M
dc.date.accessioned2024-10-09T09:50:43Z
dc.date.available2024-10-09T09:50:43Z
dc.date.issued2024
dc.description.abstractThis work investigates the effect of single and dual-k spacer materials consisting of different dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low k spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The drain induced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture's performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: ION to IOFF ratio of approximately 105 , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS FET is also analyzed with single-k and dual-k spacers. The performance of single-k and dual-k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/1614
dc.titleSpacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applicationsen_US
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