Browsing by Author "Rani, D"

Now showing 1 - 4 of 4
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    Design and Performance Analysis of ISFET using various Oxide Materials for Biosensing Applications
    (2024) Majji, S; Dash, C; Rani, D; Bhukya, M; Panigrahy, A
    The healthcare industry is always changing because of technological breakthroughs that spur new methods of diagnosing and treating illnesses. This study investigates the development of Ion Sensitive Field Effect Transistor (ISFET) sensors for DNA based blood cancer diagnosis. This work presents the design of a two-dimensional ion-sensitive field-effect transistor. Concentration fluctuations and transfer characteristics with different oxides are studied using blood from two electrolyte solutions. It is possible to evaluate how the modeled device can be utilized as a pH sensor or a biosensor in healthcare applications by looking at how the pH changes for different oxides. Additionally, several oxides were examined in the simulated ISFET devices' output characteristics. Blood is used as the electrolyte to study the device's sensitivity for different oxides. When pH 7.4 is considered, SiO2 oxide is significantly more sensitive than other oxides. The resulting 2D-ISFET exhibits remarkable blood electrolyte sensitivity and holds potential as a quick detection tool for blood cancer. The results show that the ISFET possesses drain-induced barrier lowering (DIBL), greater ON-current (ION) and switching ratio (ION/IOFF), and decreased subthreshold swing (SS). The pH sensor's sensitivity and the suggested equipment can detect up to 30 fg/mL of blood cancer biomarkers. An important development in technology-driven healthcare is the emergence of DNA-based blood cancer detection utilizing ISFET sensors. This opens up new avenues for improving cancer diagnosis and patient outcomes.
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    Performance Improvement of Spacer engineered N-type Tree Shaped NSFET towards Advanced Technology nodes
    (2024) Gowthami, U; Panigrahy, A; Rani, D; Bhukya, M; Sreenivasulu, V
    Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high-k dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with T(NS) = 5 nm, W(NS) = 25 nm, WIB = 5 nm, and HIB = 25 nm has high on-current (ION) and low off-current (IOFF). The 3D device with single-k and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual-k device achieves the maximum ION/IOFF ratio, which is 109 , compared to 107 because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device's analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL = 23 mV/V and SS = 62 mV/dec and switching ratio (ION/IOFF) = 109 . The device's performance confirms that Moore's law holds even for lower technology nodes, allowing for further scalability.
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    Simultaneous Placement of Multiple Rooftop Solar PV Integrated Electric Vehicle Charging Stations for Reliability Benefits
    (2023) Reddy, G; Rani, D; Gope, S; Narayana, B
    Electric Vehicles (EVs) are known to be future mode of transportation because of their environment-friendly nature. The increase in electric vehicle (EV) penetration needs to set up the new charging stations to meet the demand. The EV charging shows the negative impact on distribution system and system failures lead to the unavailability of power to charge EVs. The EVs not charging due to system failure is to be considered but ignored in the previous studies. Incorporating the Vehicle-to-Grid (V2G) technologies into charging station (CS) improves the system reliability. In this paper, solar rooftop PV units are integrated with CSs to overcome the negative impacts of EV charging and further enhance the reliability of the system. To extracts the maximum benefits from the solar PV integrated charging stations (PVCS), optimal placement is done with objective of reliability improvement. EV reliability is evaluated by using a novel index called as expected energy not charged (EENC). The reliability of both distribution system and EVs are considered as objective functions simultaneously, hence, placement problem becomes multi-objective. The optimal placement is done by considering different EV penetration levels. A multi-objective Grasshopper optimization algorithm (MOGOA) is applied to solve the optimal placement problem of PVCS. The EENS value is improved by 6.18% and 13.9% as compared to base case for case 1 and case 2 respectively. The EENC is improved by 11.51% in case 2 as compared to case 1.
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    Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications
    (2024) Panigrahy, A; Amudalapalli, V; Rani, D; Bhukya, M
    This work investigates the effect of single and dual-k spacer materials consisting of different dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low k spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The drain induced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture's performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: ION to IOFF ratio of approximately 105 , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS FET is also analyzed with single-k and dual-k spacers. The performance of single-k and dual-k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.